The memristive elements can be integrated with source, drain, or gate regions of buried CMOS transistors. Follow-on efforts will focus on demonstration of these hybrid structures, and electrical measurement to demonstate their utility in the simulated/modeled 1T1R and FPGA-based structures from this effort.
This effort successfully produced simulation data and code for hybrid CMOS/memristor devices. The Verilog- A and SPICE code can be used for future efforts, which could include incorporation of empirical data from device measurements. This will be critical for modeling behavior of integrated CMOS/memristor devices and ensuring that functional devices can be fabricated. The preliminary measurement data from the FPGA-routing/memristor circuits is also informative for future designs to simplify FPGA routing by incorporation of memristor elements.
This work was done by Wei Wang of the State University at Albany for the Air Force Research Laboratory. AFRL-0208
CMOS-Memristor Hybrid Nanoelectronics (reference AFRL-0208) is currently available for download from the TSP library.
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