Asymmetric Core Computing for High-Performance Applications

Methodologies and performance data were assessed relating to high-performance computing technologies for the warfighter.

High-performance computing (HPC) users have traditionally relied upon two things to supply them with processing power: speed of the central processing units (CPUs) and the scalability of the system. There are problems with this approach. Physical limitations are curtailing clock speed increases in general-purpose CPUs, the von Neumann load-execute-store approach does not map well to every computational problem, and systems of thousands of processors might be very inefficient, depending upon processor interconnection limitations. Blending asymmetric computing resources makes sense for addressing the needs relating to the U.S. Army HPC perspective. Several versatile, commodity-based options are coming online that now include throughput architectures such as graphics processing units (GPUs), reconfigurable systems built on field-programmable gate arrays (FPGAs), multi- and many-core x86-based systems, and heterogeneous systems such as the Cell processor (incorporating a standard CPU and vector processing unit). These options allow for smaller footprint systems with tremendous speed-ups compared to traditionally large clusters of von Neumann general-purpose CPUs.

The goal is to combine the asymmetric capabilities of these various cores into a complete, high-performance computing system. The primary focus is on battlespace applications to move HPC closer to the soldier and the field commander. Doing so opens up new possibilities to increase the capabilities of the soldier, and the systems being used in many application areas (e.g. sensors and intelligence applications). Algorithm development for applications needing improvements in speed and/or fidelity will be critical.

Each of these may be used to provide performance that, at one time, was only available by using Application Specific Integrated Circuits (ASICs) or large-scale, fixed HPC assets. Newer methodologies hold the hope of being more cost efficient and deployable, along with providing faster development times and allowing the use of algorithms that remain modifiable at all stages of development and fielding.

There is a fundamental change occurring in the HPC field as throughput architectures gain in importance, market share, and raw floating-point computational capacity. Portable, and even handheld high-performance computers, are quickly becoming a reality, and a concerted effort is needed to make these technologies viable for Army forces. New approaches are holding promise for moving these technologies more into the open-source arena, thus allowing researchers more direct understanding and control at low levels. These efforts should greatly facilitate the maturation of compiler and API technologies.

This work was done by Dale Shires, Song Jun Park, Brian Henz, Jerry Clarke, Lam Nguyen, and Kelly Kirk of the Army Research Laboratory. For more information, download the Technical Support Package (free white paper) at www.defensetechbriefs.com/tsp under the Electronics/Computers category. ARL-0086

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