Applying Reconfigurable Computing to Acoustic Sensors Using FPGAs

A detection algorithm is then run on the FFT output magnitudes to identify possible targets. This is done in two stages. First, a peak picking algorithm estimates the noise floor and high-power frequency bins are selected with a threshold determined from that noise floor. Harmonic line analysis is performed to find groups of frequency bins that form a harmonic relationship. Groups containing enough frequency components are declared to be targets. In the second stage, beamforming is performed on the raw data at the target’s frequencies to determine exact target bearings. Finally, a tracking filter is applied to reduce the number of false reports and provide a lock on the target’s bearing, providing lines-of-bearing (LOB) updates once every second. This entire computation could be done on either the CAµS DSP or the CAµS FPGA alone.