Compact Chip Architecture Provides High-Speed Image Processing

Friday, June 01 2007

To quickly distinguish friend from foe or make sense of a visual scene, no machine can beat the human eyes and brain — at least not yet. But a better silicon eye has been built with a series of Missile Defense Agency (MDA) Phase I and II Small Business Innovation Research (SBIR) contracts for the development of a chip with a new architecture specifically for highspeed image processing.

Computational Sensors Corporation (CSC) of Santa Barbara, CA, developed novel architectures and interconnects for massively parallel computing in a compact integrated circuit. This “alternate architecture” involves three-dimensional stacking of integrated circuits beneath a focal plane array, enabling massively parallel image processing at the pixel level.