Defense Tech Briefs - Compact Chip Architecture Provides High-Speed Image Processing

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Compact Chip Architecture Provides High-Speed Image Processing

Jun 01 2007

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To quickly distinguish friend from foe or make sense of a visual scene, no machine can beat the human eyes and brain — at least not yet. But a better silicon eye has been built with a series of Missile Defense Agency (MDA) Phase I and II Small Business Innovation Research (SBIR) contracts for the development of a chip with a new architecture specifically for highspeed image processing.

CSC’s compact, lightweight 3D stacked chip.

Computational Sensors Corporation (CSC) of Santa Barbara, CA, developed novel architectures and interconnects for massively parallel computing in a compact integrated circuit. This “alternate architecture” involves three-dimensional stacking of integrated circuits beneath a focal plane array, enabling massively parallel image processing at the pixel level.

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