| Compact Chip Architecture Provides High-Speed Image Processing |
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| Jun 01 2007 | |
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How It WorksConventional image processors typically yield data output in the megahertz range, rapidly creating a backlog of information to be sorted and analyzed. To address this backlog and to prepare for high-speed operations — both of which are needed for missile threat discrimination — CSC stacked integrated circuits beneath a two-dimensional detector array. This very-large-scale integration (VLSI) approach enables the chip to perform the image processing onboard the circuitry, and avoid the customary bottleneck at the tail end of the processing stream. The result is a fast, low-power imaging device that boasts a small footprint and light weight. CSC’s chief innovation is the stacking architecture that eliminates the bottleneck experienced in conventional digital image processing. In turn, the rapid processing capability enhances the ability of an imaging device to perform threat assessment in real time, and to track and identify multiple targets against background clutter. The new architecture was an extension of CSC’s previous MDA-funded thin-film analog processor development, and was designed to pass pixels through the computational process without storing (and therefore slowing) the information provided by the sensor. The resulting capabilities are termed neuromorphic, or comparable to biological or “intelligent” systems, where image processing at the neural level is done on the fly. In this way, the full spectral range of the sensor can be utilized efficiently, with a better signal-to-noise ratio and alias-free operation.Collectively, CSC’s MDA-related
innovations have helped to improve
automatic target recognition, target
tracking, feature extraction, 3D
reconstruction, image classification,
and image understanding — parameters
that comprise the underpinnings
of compact, low-powered,
deployable missile defense systems. |
