Home arrow Tech Briefs arrow Information Sciences arrow The Dataflow Interchange Format for Designing DSPs
The Dataflow Interchange Format for Designing DSPs Print E-mail
Defense Advanced Research Projects Agency, Arlington, Virginia   
Sep 30 2007
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The DIF language is designed as a standard language for specifying DSP oriented dataflow graphs. The DIF language provides a unique set of semantic features to specify graph topologies, hierarchies, and dataflow-related and actor-specific information. DSP applications specified by the DIF language are usually referred to as DIF specifications. The DIF is implemented by means of the DIF package, which is a Java software package that has been (and continues to be) developed along with the DIF language.

Other developments pertaining to the DIF, applications thereof, and related applications include the following:

  • A DIF-based methodology has been conceived as a systematic approach for porting DSP designs across design software tools and libraries. The combination of this DIF-based porting methodology and the porting infrastructure provided in the DIF package is intended to enable the efficient migration or development of DSP designs across the tools and libraries. Such migration or development would be equivalent to porting DSP designs across the underlying embedded processing platforms that are supported by the software tools and libraries.
  • A DIF-to-C software-synthesis framework provides for automatic generation of C-language software from high-level dataflow specifications of DSP systems. The DIF-to-C framework integrates scheduling, buffering, and code-generation techniques and enables association of dataflow actors with their desired C-language functions. In other words, the DIF-to-C framework offers a useful link between coarse-grain dataflow optimizations and manually optimized libraries, and provides an efficient way to explore the complex range of tradeoffs in the implementation of DSP software.
  • A simulation oriented scheduler (SOS) algorithm and software that implements it have been developed to solve major problems encountered in simulating highly multirate systems. The SOS scheduler emphasizes effective, joint minimization of time and memory requirements for simulating critical synchronous dataflow graphs (SDFs). In tests of the SOS software, large reductions in amounts of time and memory needed for simulating large-scale and highly multirate wireless communication systems have been demonstrated.
  • A multithreaded simulation scheduler has been developed as a means of reducing simulation time by exploiting multithreaded execution of SDF graphs on multi-core processors. In tests on a commercial dual-core hyper-threading processor comprising four processing units, speedups by factors as large as 3.5 were obtained in simulations of modern wireless communication systems.

This work was done by Chia Jui Hsu of the University of Maryland for the Defense Advanced Research Projects Agency.

This Brief includes a Technical Support Package (TSP).

The Dataflow Interchange Format for Designing DSPs (reference DARPA-0006) is currently available for download from the TSP library.

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