Radar receiver design is seeing an increase in the number of digital tuning and digital signal processing (DSP) functions moved from back-end single-board computers into fixed front-end hardware logic. The front-end receivers have become much more complex and difficult to design. This results in two rising challenges for digital design engineers: prototyping and testing highly sophisticated receivers, and designing with limited budgets for both power and heat dissipation.

Structured ASICs are made up of custom top layers and standard base layers.

FPGA-to-ASIC transitions have been exercised for the past two decades by many digital logic designers based on changes in market requirements, or when systems transition from prototype to fixed configuration, full production. The cost and schedule successes of these transitions depend on complexity, tolerances, and the working relationship between FPGA designers and ASIC designers.

Where the advantages of making this transition from FPGA to structured ASIC in a system are usually evident, the cost and risk of making this transition are the deciding factors for engineering managers. Once these costs are both predictable and low, sensor board designers can confidently make FPGA-versus-ASIC decisions as part of their standard design flow.

Prototyping Radar Systems

The National Missile Defense Ground Based Radar Prototype (NMD-GBR-P) is an example of a long-lead radar prototype program. The NMD-GBR-P was designed to prove out active and passive array technology for missile defense. This program also sought to test and develop the intricate integrated activities of tracking, C4I, and battle damage assessment of a missile defense system, as well as reduce system risk. From FY 1996 to 2004, over $200 million was spent on the radar prototype alone.