Distributed sensor systems and radar data fusion are other areas where prototyping and iterative design changes are essential. These applications are driving more sophisticated modeling systems, and are well-suited to FPGA and “blue board” prototypes. These early prototypes also help software developers innovate with better algorithms and software tactics for best-fit detection and tracking, such as Space-Time Adaptive Processing (STAP). As an additional benefit, prototypes allow designers to innovate architectural improvements to increase the maintainability of the system for increased design life.

FPGA-to-ASIC Die Change

Large-scale multi-use radars, such as the Multifunction Phase Array Radar (MPAR) concept, will certainly require a large degree of multi-mission prototyping. Such a radar system, if implemented across several national radar missions, will also benefit from enough receiver card volume to see per-unit cost advantages from structured ASIC design approaches.

The roles of the researchers and laboratories have become prominent in radar systems development, as they have a greater set of responsibilities in helping to make systems sustainable, testable, and fieldable. Architecting a solid FPGA-to-ASIC system design transition is one way to contribute.

What is a Structured ASIC?

A structured ASIC has application-specific upper layers, often designed based on an FPGA netlist. A structured ASIC is intended to fill the needs of programs that require price and performance points between FPGAs and standard-cell ASICs or ASSPs (application specific standard products). FPGA vendor Altera Corp. offers services to transition a customer's FPGA design into a HardCopy structured ASIC. The process of transitioning an FPGA design to a structured ASIC involves an extensive library of HCell macros. Each of these have been pre-characterized and pre-verified. These map logic from the FPGA adaptive logic modules (ALMs) into ASIC gates, using only the logic specified in the FPGA design. This is done without modifying the FPGA design or netlist in any way; the FPGA routing information is preserved in the design.