The structured ASIC approach has several advantages over the traditional standard-cell ASIC transition that has been conducted in the past for military sensor systems. The primary advantage is having a single vendor offering technical assistance in FPGA design, as well as transitioning to a structured ASIC. Second is the guarantee of both package and pin compatibility between FPGA and ASIC. Power estimates can be performed on FPGA and structured ASIC using the same power estimation tool. Finally, the most important reason to consider the structured ASIC design path is about risk management. A standard cell ASIC is an engineering effort with high hardware expenditures in the case of errors in chip layout, while the risks of error in transferring an FPGA netlist to the structured ASIC netlist are virtually non-existent.

Transition from FPGA to ASIC

Functional Comparison of Standard Cell ASIC vs. Structured ASIC

Miniaturization and cooling challenges are making size and power into critical design parameters. Therefore, a cost-versus-benefit trade of migrating a prototype design from FPGA-to-ASIC should be made when moving from prototype to manufacturing and deployment.

It is important to note that the decision to pursue the receiver electronics design in an FPGA flow does not require any initial design constraints for the FPGA designer. The decision to transfer to a structured ASIC design can be made well into pre-production, after all prototyping, proof-of-concept, and algorithmic testing is performed using the FPGA design and test bench.

The advantages of this transition from FPGA-to-ASIC allow system design to become more compact, as the FPGA footprint and cooling requirements are reduced. However, the transition does not require a receiver board re-spin, as the structured ASIC can be designed as a pin-for-pin replacement for the FPGA in the same package.