Magnetic Memory Devices for Embedded Computing

Air Force Research Laboratory

Wednesday, October 01 2008

These devices could be utilized in novel, energy-efficient, radiation-hard electronics.

A program of research has been dedicated to the development of magnetic memory devices than can be incorporated into complementary metal oxide/semiconductor (CMOS) integrated circuits, wherein these devices can be made to function as radiation- hard logic elements and as components of small random-access memories. The goal of this development was not to provide for large-scale, bulk memories, but, instead, to provide for latches and flip-flops that can serve as state and data registers for sequential logic and as configuration registers for configurable logic. A major benefit afforded by these devices is the ability to retain the logical state of a subsystem that contains the devices when turning off the power to that subsystem to save energy until operation of the subsystem is required. The subsystem can then be powered up and begin operating within a time of the order of milliseconds.

The basic element of a device of this type is a magnetic tunneling junction (MTJ) cell. The research has been focused on refinement of such cells to make them practical for integration into CMOS circuitry, to develop CMOS circuits that contain such cells, and to integrate the fabrication of the cells into a CMOS-integrated-circuit- fabrication process.

A basic MTJ cell, shown in Figure 1, includes the following four layers: (1) a “pinning” layer made of an antiferromagnetic material; (2) a “pinned” layer of fixed magnetic orientation, made of a ferromagnetic material; (3) an ultrathin barrier layer made of an electrically insulating material; and (4) a “free layer” made of a ferromagnetic material that may differ from the material of the pinned layer. The free layer can be placed in one of two magnetization states: parallel or antiparallel to the magnetization of the pinned layer. When the magnetic fields of the pinned and free layers are parallel, then by virtue of spin-polarized quantum-mechanical tunneling of electrons, the electrical resistance through the stack of layers is less than it is when the magnetic fields of the free and pinned layers are antiparallel. The two magnetization/resistance states can be used to represent logical 1 and 0, respectively. Readout circuitry associated with the cell utilizes the difference in electrical resistance to distinguish between the two logic states.

The free magnetic layers in the MTJ cells developed in this program have shapes belonging to a patented class of shapes denoted generally and informally by the term “PacMan” because of their resemblance to a character in the popular video game “Pac-Man” (see Figure 2). Through experimentation, these shapes were chosen, along with sizes and material compositions, to obtain magnetic and electric properties superior to those imparted by prior MTJ shapes. Desirable properties include high selectivity for addressing individual cells, high reading and writing speeds, large changes in resistance, long lifetimes as measured in numbers of switching cycles, narrow distributions of switching magnetic fields and associated writing electric currents, thermal stability, and small cell-to-cell differences in the aforementioned properties. The cell designs developed in this program lead to high repeatability and high fabrication yield, making it possible to design circuits to generate the necessary switching magnetic fields predictably and reliably.

Thus far, two types of data-storage circuits incorporating magnetic memory devices of this type have been designed: a differential magnetic flip-flop and a magnetic flip-flop that could be used as a shadow random-access memory. Integration of the fabrication of MTJ cells into a CMOS-integrated-circuit-fabrication process has proved elusive because of difficulties in creating metal surfaces smooth enough to accept the cells. It will be necessary to overcome this difficulty in order to carry out the next phases of the research — to develop accurate computational models of the electronic circuitry, to implement a one-wire writing scheme that is a common feature of the designs of the flip-flop circuits mentioned above, and finally, to integrate MTJ cells with CMOS circuitry.

This work was done by Gregory W. Donohoe and Kenneth Joseph Hass of the University of Idaho for the Air Force Research Laboratory.
AFRL-0076